1. Field of the Invention
The present invention relates to a sample hold circuit for sampling and holding an instantaneous value of an analog signal, and more specifically to a sample hold circuit which is suitable to an integrated circuit and which can sample and hold a high speed analog signal.
2. Description of Related Art
One typical example of this type sample hold circuit is disclosed in, for example, U.S. Pat. No. 4,806,790.
Referring to FIG. 1, there is shown a conventional sample hold circuit shown in FIG. 2 of U.S. Pat. No. 4,806,790. The shown sample hold circuit includes a transistor Q11 having its base connected to an input terminal 11 and its collector connected to a high voltage supply terminal 15, series-connected diodes (D11 to D13) having its cathode side connected to an emitter of the transistor Q11, a constant current source I14 having its one end connected to an anode of the diode D13 and its other end connected to the high voltage supply terminal 15, and a differential circuit 31 including a differential pair of composed of one transistor Q14 having its collector connected to the emitter of the transistor Q11 and another transistor Q15 having its collector connected to the anode of the diode D13, and a constant current source I11. The shown circuit also comprises a diode D14 having its cathode connected to the anode of the diode D13, and its anode connected to a bias voltage terminal 17, a transistor Q12 having its base connected to a connection node between the diodes D13 and D14 and its collector connected to the high voltage supply terminal 15, and a differential circuit 32 including a differential pair of composed of one transistor Q16 having its collector connected to the high voltage supply terminal 15 and another transistor Q17 having its collector connected to an emitter of the transistor Q12, and a constant current source I12. Furthermore, the shown circuit comprises a hold capacitor CH having its one end connected to the emitter of the transistor Q12 and its other end connected to ground, and an emitter follower 33 composed of a transistor Q13 having its base connected to the hold capacitor CH and its emitter connected to an output terminal 12 and a constant current source I13.
Now, operation of this conventional sample hold circuit will be described.
In a sample mode in which an input voltage Sin on a control input terminal 13 is at a high level ("H") and an input voltage Hin on a complementary control input terminal 14 is a low level ("L"), the transistors Q14 and Q17 of the differential transistor pairs (Q14 and Q15) and (Q16 and Q17) are rendered conductive, and the transistors Q15 and Q16 are rendered non-conductive.
At this time, the analog signal Vin on the input terminal 11 is applied to the base of the transistor Q11, so that the transistor Q11 operates as an emitter follower. The series-connected diodes (D11 to D13) connected to the emitter of the transistor Q11, acts as a level shift circuit supplied with a current from the constant current source I14 Incidentally, a current of the constant current source I11 is a sum of the current of the constant current source I14 and an operating current of the transistor Q11. The transistor Q12 operates as an emitter follower, so that the hold capacitor CH is charged or discharged. The transistor Q13 receiving the voltage of the hold capacitor CH as an input, operates as an emitter follower, so that an output voltage Vo is outputted from the output terminal 12.
Now, assuming that a base-emitter voltage of the transistor Q11 is VBE11, a base-emitter voltage of the transistor Q12 is VBE12, a base-emitter voltage of the transistor Q13 is VBE13, and a forward direction voltage drop VF11 of the diode D11, a forward direction voltage drop VF12 of the diode D12, and a forward direction voltage drop VF13 of the diode D13, are the same voltage "VD", the output voltage Vo can be expressed as follows: EQU Vo=Vin-(VBE11+VBE12+VBE13)+3VD
Here, if it is set that all current densities of the transistors Q11, Q12 and Q13 and the diodes D11, D12 and D13 are equal, the following equation holds: EQU VBE11+VBE12+VBE13.apprxeq.3VD
In this case, therefore, the relation becomes Vo=Vin, and accordingly, the output voltage Vo follows the input voltage Vin.
In a hold mode in which the input voltage Sin and the input voltage Hin are brought to the low level ("L") and the high level ("H"), respectively, the transistors Q14 and Q17 are rendered off, and the transistors Q15 and Q16 are rendered on. In this condition, the transistor Q12 which had operated in the emitter follower fashion in the sample mode so as to cause to charge or discharge the hold capacitor CH, is rendered non-conductive as a result of the conducting of the diode D14, so that the charge/discharge operation is stopped and an instantaneous value of the voltage Vin+VD is held in the hold capacitor CH.
Thus, an instantaneous value of the input voltage Vin is held and outputted from the output terminal 12. Incidentally, a condition of cutting off the transistor Q12 is sufficient if a sum of the potential of the hold capacitor CH and the base-emitter voltage VBE12 of the transistor Q12, namely, the base potential (Vin+2VD) of the transistor Q12 is larger than a voltage obtained by subtracting the forward direction voltage drop VF14 of the diode D14 from the voltage of the bias voltage terminal 17. Here, assuming that the voltage of the bias voltage terminal 17 is VB, and the forward direction voltage drop VF14 of the diode D14 is equal to VD, the above condition can be expressed as EQU VB-VD&lt;Vin+2VD
As one example, assuming that the analog input voltage Vin takes a value in the range of -2 V to 0 C, since VD is generally on the order of 0.7 V to 0.8 V, it is sufficient if the bias voltage VB is on the order of 0 V (ground potential). On the other hand, the above condition can be satisfied by connecting the terminal 17 in common to the high voltage supply terminal 15, and replacing the diode D14 by a plurality of diodes.
However, the above mentioned sample hold circuit is disadvantageous in that the condition for holding the input voltage depends upon the input voltage, and a non-linear characteristics of the circuit becomes large.
In other words, the cut-off condition "VB-VD&lt;Vin+2VD" of the emitter follower transistors Q12 can be modified as follows: EQU VB-3VD&lt;Vin
Accordingly, it is disadvantageous in that the range of the input voltage that can be held in the sample hold circuit, is limited, and the cut-off condition of the transistors Q12 depends upon the input voltage.